A Practical intro to programming an open source SoC
A post-event report from Open Source Hardware User Group meeting No. 17.
At the seventeenth OSHUG meeting we were given an introduction to the practicalities of programming your own open source system-on-a-chip (SoC), based upon using the OpenRISC Reference Platform SoC (ORPSoC) targeted to an FPGA development board.
SoC integration, IP blocks and HDL
The evening's proceedings started with Julius Baxter explaining how there has been a shift over the last 20 years from building systems out of many discrete ICs, to integrating entire systems on a single semiconductor die. These on-chip systems being made up of many intellectual property (IP) blocks that are analogous to discrete components and that are designed for maximum reuse, and which may be developed in-house by a SoC integrator, or licensed from a 3rd party.
Julius then went on to cover how the the IP blocks are connected together via an on-chip bus, and talked a little about the hardware description languages (HDL) that are used to develop blocks, and how these languages differ from those that are typically used in software development.
A closer look at OpenCores and OpenRISC
Next up was Jeremy Bennett, who previously gave us a high level introduction to the OpenCores community, chip development and OpenRISC at OSHUG #9. This time Jeremy explored the OpenRISC 1000 architecture and its first implementation — the 32 bit OpenRISC 1200 with FPU and MMU support — in more detail. And introduced the ORPSoC reference platform for the processor, which uses the Wishbone bus to integrate a selection of peripherals such as UARTs etc, to create a basic system that is capable of booting Linux.
From debug to ASIC
Julius briefly returned to the stage and explained how the ORPSoC platform supports debugging via JTAG and GDB, and also mentioned that a multicore OR1200 design is due for release soon and that work is under way for LLVM support. Julius concluded this part of his presentation by explaining how Samsung make use of OR1200 in a DTV set top box ASIC, and how they have contributed back to the project by making their modifications to the OR1200 design available!
Building an OpenRISC-based PC
A welcome last minute addition to the agenda came next, as an MSc student from Southampton University took the stage to tell us about their project to build a PC based upon the OR1200. At the present time having already integrated VGA, an SDRAM controller and a PS/2 interface, and an SD card controller and support for booting from SD being next on their to-do list.
Julius returned to the stage with a series of demonstrations, the first of which involved booting the ORSoC via a simulator, and then inspecting processor signal lines via the Gtkwave tool as it ran a very simple program. Next Julius covered the process of adapting ORSoC for use with different FPGA development boards, and talked in more detail about debugging. In closing he went on to demonstrate a Xilinx ML501 board loading a synthesized ORPSoC design from system flash, which then proceeded to execute the U-boot boot loader, which in turn booted Linux and dropped into a BusyBox shell prompt.
This was the first time that we had dedicated an entire 90 minutes to a single topic, but judging from the interest demonstrated by attendees, and by the excited discussions taking place in the pub afterwards, this will not be the last time that open source chip design is the focus of an OSHUG meeting.
To download the presentation click here.
With thanks to DesignSpark for sponsoring OSHUG No. 17!