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7 Jan 2019, 15:52

What is the top design challenge for IoT and wearables applications?

The Internet of Things and wearables revolution has changed everything. By everything, we mean everything. From size and connectivity requirements to firmware and integration challenges, the new world of IoT and wearable designs brings many changes. New requirements ripple through the technology supply chain, such as semiconductor design, passive components, software and cloud.  More than any other new requirement, lower power consumption is pervasive throughout. The need to survive remotely from small batteries or even from harvested environmental energy has become greater than ever and affects the entire development.

The key to ultra-low power design is addressing the parts of the circuit that are continuously active. Most devices conserve power by deactivating the majority of functions and entering a deep sleep mode. A low duty cycle of activity enables most IoT and wearable designs to stretch battery life while still executing tasks. A 10% duty cycle multiplies battery life by 10, and some applications can comfortably use a 1% or lower duty cycle.

Engineers have always used this trick to conserve power. However, it has limitations. IoT and wearable applications need to know when to wake up and do their work. Human intervention is not guaranteed, so the device requires self-awareness. Thus, an active part of the circuit must run nonstop, even in deep sleep. This activity sets a ceiling on battery life. The IC design must starve continuously active circuits of power in order to meet the battery life requirements of the application.

Since the real-time clock (RTC) and other 32.768kHz circuits remain unceasingly active, these timing components have adapted the most power-constrained IoT and wearable applications. Always on, the 32.768kHz signal acts as an essential heartbeat, managing critical functions like power switching, alerts, interrupts, and most importantly, wake up. So it cannot be turned off.

Conserving power requires this essential circuit be designed with lower transconductance gain (gm). A lower gm means that the oscillator circuit cannot drive heavily plated crystals with a high equivalent resistance (ESR). The semiconductor circuit and the quartz crystal must both adapt to a lower power design. Thus, IoT- and wearable-optimized crystals must be designed to meet lower plating capacitance (CL) with a well-controlled lower ESR across temperature. Otherwise, new MCUs and RF chipsets designed specifically to address the need for lower power on next-generation semiconductor processes will not be able to drive them. Generous transconductance gain within the oscillator driver circuit is now a luxury of the past.

So what is the top design challenge for IoT and wearables? There is little doubt that it is power consumption. Miniaturization, integration and other system issues are present. However, the way devices are designed must first meet a power consumption ceiling, or else the product cannot meet the battery-life requirements of IoT and wearable systems. Clocking and quartz crystals have adapted well to this new need.

The attached whitepaper discusses how to reduce oscillator power consumption while achieving optimal oscillation margin - using quartz crystals designed to mate with energy-saving low power SoC’s. The included measurements demonstrate the key principles that are essential for the design of a reliable, low-power oscillator - download below.

Seasoned Engineering Executive with over 25-years experience in Frequency Control Products. Experience includes design and application of Quartz Crystals, Oscillators (XO, TCXO, VCTCXO, OCXO, Stratum-III), PLL's, Lumped Element & Cavity Filters, RF Amplifiers, etc.

7 Jan 2019, 15:52