The Journey to CE Marking an IoT Product Part 3: Design ReviewFollow article
This series of posts follow the progress of taking an IoT product from prototype, through testing and design revision as required, in order to allow CE marking for general sale.
In part 1 we introduced the Environmental Sensor project that would be the focus of this blog post series and gave a very short summary of CE and the overall process. In part 2 we heard from James Pawson of Unit 3 Compliance, via a series of videos that provided a little more detail on exactly what CE is, along with EMC and the importance of considering this from the beginning.
In this post we take a look at the first step in our journey proper: initial design review.
We could send our functional prototype straight to a pre-compliance lab, or if we are feeling particularly confident, for accredited lab testing. However, both courses of action could mean incurring additional costs — and at a much faster rate with an accredited lab — which might have been mitigated if we had an expert review the design prior to commencing lab testing.
In our case we had built two versions of the PCB and with the second, CAD v2, we had built a total of 30 fully functioning boards in-house, on a small prototyping assembly line. Hence at this point we were happy with the design from a functional perspective and those boards had been put through their paces, having been installed on-site and running 24/7 for a number of months, without issue.
So we sent our DesignSpark PCB database off to Unit 3 Compliance — and crossed our fingers!
It didn’t take long before we heard from James and next we’ll take a look at his recommendations.
There were three suggested areas for schematic improvements.
“Microphone circuit currently has nothing to limit the AC gain. This means that if noise is coupled in to the circuit from the EMC immunity tests then it could cause false readings. Limiting AC gain of analogue circuits is often key to god immunity performance. To remedy this I would:
- Add a DNI capacitor in series with R39 and R40 to enable this to form a bandwidth limiting network in the feedback of each amplifier.
- The junction of R19/R20/U5.6 add a DNI capacitor to ground from this node to allow a low pass filter to be constructed by R20 and the new capacitor without affecting the desired audio bandwidth
This allows fitting of these components should problems be found in testing and production can be adjusted with a BOM change to the provisioned components rather than performing another CAD cycle and having to scrap previously made boards.”
Sage advice indeed and as Karl, the original designer of the board, liked to note, circuits are cheap! In other words, you can typically add just-in-case footprints for additional components which are initially marked DNI — do not insert. Then if it turns out that you do need extra decoupling, filtering or limiting etc., you can later populate those footprints during testing. Whereas without such provisions, uglier fixes will be called for and ultimately, you will need to spin a new board.
PL1 and J1
“The serial port connector PL1 and the expansion header J1 are risk items as they can connect to the outside world through cables (or "antennae" as they are known in EMC circles) which means they can both radiate or pick up noise. They will be susceptible to Electro Static Discharge (ESD) and noise injection. To mitigate this, I would add a DNI capacitor from the following pins to GND to allow provision for filtering if found to be necessary:
- PL1 pins 3 (P0/RX0) and 2 (P1/TX0)
- J1 pins 1, 2, 4, 7, 8, 9, 10
- add a 0R0 resistor in series with the 3V3 net and pins J1.6 and J1.12
- add a 0R0 resistor in series with the 3V3 net and pin PL1.4
- add a 100n capacitor to ground from pin PL1.4 for extra decoupling, to allow the fitting of a ferrite bead filter if required”
Once again excellent advice. Our CAD v2 boards may have performed perfectly well at the installation site, but the J1 expansion port wasn’t being used at all here and while PL1 is a serial port typically used only during development, some applications may have a use for it.
“The EMC performance of PIR sensor is often linked to noise on the power supply rail. I would consider adding a low pass filter formed by a 33R resistor between 3.3V and U4.3 and a 100n decoupling capacitor (or whatever you are using on the board) to ground from U4.3”
A simple enough to implement precaution and a small cost for improved sensor performance.
We have three recommended changes again in terms of layout.
“The traces that run from the Pycom module around the bottom right of the board run a little too close to the edge for comfort. Traces near the edge of the board can appear like antennae so I would look to move these inboard so that you've got at least a 3mm no trace zone all around the edge. Moving the LEDs should let you achieve this fairly painlessly.”
This is highlighted in the above image.
Microphone Reference Voltage
“I would recommend that the microphone reference voltage trace from the end of R24 be rerouted. Currently it travels a long way around the bottom left edge of the board and for a high impedance analogue net this isn't a good plan. I suggest a minor re-route”
See the image above for this change.
“As per recommendation #3 in the schematics section, provide a separate power feed from the main 3V3 net for the PIR sensor”
So now we have our list of recommended changes that can be used as inputs to the next spin of our sensor board design. If we are lucky, with these changes incorporated, we will be able to get through pre-compliance, with at most having to populate some of those DNI positions.
The design was originally put together for an internal use project and so CE wasn’t a consideration. However, if it had been, we could have possibly saved time and money by having the design reviewed prior to the CAD v2 build. We could have even done this before assembling v1 boards, but then there is always the possibility that the design didn’t meet our functional requirements or even work at all, so this is a question of timing.