SPI Communication and Common IssuesFollow article
I was working on an application on some EFM8 MCUs and was having some Serial to Peripheral Interface (SPI) issues. After some debugging and bringing out the logic analyzer I learned that my clock speeds were not within spec for that specific MCU. To save you guys future trouble I have outlined what I figured out while debugging the issue and hopefully it can help you!
SPI clock speed and limits
When configured as a SPI master device, the maximum C8051 SPI clock frequency that can be realized is dependent on the system clock frequency (SYSCLK). For most devices, the maximum SPI clock frequency is one half of the system clock, but cannot exceed 12.5 MHz. Thus, as long as system clock frequency is 25 MHz or higher, the SPI clock can operate up to 12.5 MHz, and at system clock speeds below 25 MHz, the maximum SPI clock rate is SYSCLK/2. Below is a shot from the logic analyzer I was using, as seen I was able to send data to the slave(MOSI) but was getting nothing back on the return line (MISO) .
When the SPI is configured in slave mode (i.e. the SCK is driven by the master), the maximum data transfer rate is 1/10 of the slave system clock frequency for most devices, provided that the SPI clock, NSS, and data lines are driven synchronously by the master. If these signals are asynchronous with respect to the slave device, the data transfer rate must be less than 1/10 the system clock frequency of the slave device.
For specific information on a device, consult the SPI documentation in the device data sheet or reference manual.
For example Silicon Labs EFM8 Busy Bee devices have this in the reference manual
Below is the actual EFM8 kit that I was using.
SPI clock configuration
Another very common SPI problem that I incorrectly thought was my original issue is clock polarity and phase. These two parameters control when the slave or master pulls in data. the two configurable parameters lead to a total of 4 total combinations that must be set up by the master in order for correct communication to occur. The clock phase and the polarity together control whether the data is latched on the rising or falling edge as well as the default or starting state of the clock. Below is an illustration showing the clock waveform combinations and showcasing when the data is sent through. Seeing when the data is latched (red line) it is easy to understand that if the master does not set up the polarity and phase to what the slave expects, both commands and data will be incorrectly read by the slave.
I hope by reading this you have gained a better understanding of how SPI communication is configured and a couple nuances that it has. If you have any more questions feel free to message me or comment!