SiC MOSFET Gate-Driver Design for Best Efficiency and ReliabilityFollow article
Getting the best from silicon carbide power transistors calls for switching frequencies up to five times higher, and gate-voltage excursions up to two times greater, than typically applied to silicon-based alternatives. Designing a suitable gate-driver requires careful attention to transient effects and parasitic capacitances.
Silicon carbide power MOSFETs are moving closer to approximate price parity with conventional silicon MOSFETs or IGBTs. Their key advantages are lower RDS(ON) and reduced switching losses, breakdown voltages comparable to IGBTs, and greater temperature capability. These give designers of power-conversion systems such as switched-mode power supplies or inverters more freedom to increase energy efficiency, specify smaller components, and simplify thermal management to minimize size and engineering costs without sacrificing reliability.
Paying careful attention to the design of the gate driver, to ensure optimal performance in the ON state and during switching transitions, is important to maximize these inherent advantages of SiC MOSFETs.
Secrets of SiC Success Bring Switching Challenges
The high breakdown voltage of SiC MOSFETs is the result of the wider bandgap of SiC compared to conventional silicon. Because the electrons require about three times higher energy to move from the valence band to the conduction band, this ultimately allows a SiC MOSFET to withstand about 10 times the breakdown field strength of a comparable silicon device. Regarded from the opposite perspective, the channel thickness can be greatly reduced for a given voltage rating, which results in a lower minimum RDS(ON).
However, SiC MOSFETs behave differently in saturation compared with silicon devices. There is no clearly defined transition between the linear and saturated regions: whereas a silicon MOSFET is more or less turned fully on when VGS exceeds the threshold voltage - causing the device to behave like a non-ideal current source - the SiC MOSFET has generally lower transconductance (gm) and instead behaves more like a variable resistance. The result is that RDS(ON) continues to reduce as the gate voltage is increased towards the maximum allowable limit, VGSmax. Hence, a higher turn-on gate voltage is required to fully realise the superior RDS(ON) of the SiC MOSFET. Because VGSmax can be about 18-25V, depending on the device, the driver must be capable of applying VGS in the range of 15V to 20/22V.
As far as the switching behaviour is concerned, the SiC MOSFET - as a majority-carrier device - inherently has no turn-off tail current. This is unlike a silicon IGBT, which utilises minority-carrier injection to modulate conductivity and so achieve excellent conduction characteristics but on the other hand exhibits a tail current at turn-off as the minority carriers (holes) recombine. The recombination time limits the maximum possible switching frequency, and the tail current existing at the same time as the voltage across the IGBT is at its maximum increases switching losses. SiC MOSFETs, having no tail current, can operate at higher switching frequencies without suffering high energy losses, while device breakdown voltages can be comparable to those of IGBTs. In practice, SiC devices can support switching frequencies two to five times higher than silicon IGBTs, which permits the use of smaller passive components.
The switching requirements of SiC MOSFETs place extra demands on the driver circuitry. Not only must the driver generate a higher VGS to turn the device hard on and so minimise RDS(ON), but a fast output slew rate of several volts per nanosecond, with high current sink/source capability, are needed to maintain the high VGS while charging and discharging the gate-circuit capacitances quickly. Fast edges and rapid charge movements present designers with hazards such as overshoots and ringing, and potentially large unwanted voltage transients that can cause spurious switching of the MOSFETs.
To achieve a fast transition to VGS of about 15-20V needed to turn the MOSFET on, the driver must source a high current to charge the gate capacitance quickly and complete the turn-on process within about 10ns. This current can be mostly supplied from a bulk capacitor in the gate driver, and passes through the driver’s internal resistance and the resistances associated with the MOSFET gate circuit. The internal gate resistance of some SiC MOSFETs is an order of magnitude higher than in a conventional silicon device, which combines with the gate capacitance to produce a large RC time constant and so demands a high current to switch the device quickly. Figure 1 illustrates current flow during the turn-on phase .
Figure 1. A large driver source current is needed to charge gate capacitances quickly. Source: ON Semiconductor TND6237/D .
To simplify the turn-on arrangements, a low maximum VGS (VGSmax) is a desirable device parameter. This enables relatively simple driver circuitry to turn the device ON, and achieve low RDS(ON), while giving good immunity to the possibility of unwanted turn-on when the device is required to be held off.
At turn-off, the absence of tail current means that turn-off energy (Eoff) is dissipated only during the short overlap between falling drain current and rising VDS. Minimising this overlap is central to achieving the lowest possible Eoff, and requires the charge to be extracted from the MOSFET gate as quickly as possible.
In a single-switch topology, such as a boost, buck, or flyback converter, controlling the gate to turn the device off as quickly as possible is relatively straightforward. Applying a negatively biased VGS, with an external gate resistance of only 1Ω-2Ω promotes rapid flow of charge out of the gate, turning the device off quickly.
The applied gate-source voltage is also responsible for holding the MOSFET off until the next turn-on cycle. Considering that SiC MOSFETs have relatively low gate threshold voltage, VTH, a small amount of ground bounce could cause a positive bias of VGS exceeding VTH, if the gate driver is not designed to generate negative gate voltage. Hence, in addition to aiding fast turn-off, a negative bias on VGS provides greater immunity to unwanted turn-on.
In converters that have high-side and low-side MOSFETs, such as LLC, half−bridge or full−bridge topologies, switching the high-side or low-side device can produce dVDS/dt transients across the other device. This is a familiar effect in MOSFETs of any type, which can produce unwanted turn-on by causing gate currents to flow through the device’s parasitic CGD capacitance. Here, again, negatively biasing VGS provides extra protection against spurious turn-on that can otherwise impair the efficiency of the converter.
The driver should have low output impedance so as not to limit the current that can be driven into the MOSFET input capacitance, Ciss. A low impedance output gives designers more flexibility to control dVDS/dt transients by adjusting the resistance RG in the external gate circuit and so avoid unwanted switching.
For turn-on, RG should be a low value of just a few Ohms, to charge Ciss quickly. On the other hand, excessively low RG relative to the external gate resistance of the other MOSFET, which is turned off, can cause the device to turn on and so incur unwanted switching losses. The RGON of one device should be greater than the RGOFF of the other.
Figure 2. Implementing separate turn-on and turn-off gate resistance values for unwanted turn-on avoidance. Source Infineon AN2017-04 .
Separate RGON and RGOFF circuits can be implemented for each MOSFET. Figure 2 shows how this can be done using two types of drivers from Infineon’s EiceDRIVER™ family . The 1EDI-C driver on the left has separate source/sink outputs, while the schematic on the right shows a driver from the 1ED-F2 family that has a single output with negative turn-off voltage capability.
In an application note about fine-tuning SiC MOSFET gate drivers , STMicroelectronics recommends making RGON at least 1.5 times RGOFF, with resistance values of about 4.7Ω and 2.2Ω respectively.
Other Desirable Driver Features
Close delay matching
Properly managing the interactions between high-side and low-side devices during switching transitions introduces additional challenges such as ensuring adequate dead-time to prevent both devices being ON at the same time, and so prevent shoot-through currents that are as dangerous for SiC MOSFETs as for conventional silicon devices. The higher switching frequencies of SiC converters call for very short dead time. This, in turn, requires the propagation delays between high-side and low-side gate drivers, and between the high-side and low-side MOSFETs themselves, to be closely matched. In this respect, the propagation delays are more significant than the rise and fall times.
It is possible to design a driver using discrete circuitry, capable of applying suitable turn-on and turn-off voltages, and of sinking and sourcing high current to charge and discharge the gate circuit quickly through small turn-on and turn-off gate resistances. However, other desirable features such as desaturation protection are more complicated to design.
Fast Desaturation Protection
SiC MOSFETs can be more difficult to protect against over-current hazards than silicon-based devices. An IGBT, for example, operates in a clearly defined saturation region when conducting normally, and is driven out of saturation into the linear region in the event of an over-current. This is characterised by rapidly increasing collector-emitter voltage, Vce, which is relatively easy to detect as a trigger to activate over-current protection.
In contrast, the SiC MOSFET operates in a linear region where VDS changes more slowly, even as ID rises. Hence an over-current condition can prevail for several switching cycles before a measurable change in VDS occurs, which can be enough to cause damage to the device. For this reason, designing a fast-acting desaturation-detection circuit that also has high immunity to false triggering is difficult, and further complicated by fast switching speeds that cause additional noise during turn-on transitions. A gate-driver IC that contains fast desaturation detection circuitry, such as the Infineon EiceDRIVER™ 1ED-F2 family or the ON Semiconductor NCP51705, can overcome this hurdle and also provides suitable gate voltages, turn-on protection mechanisms such as active miller clamping, and other features such as under-voltage lockout and filtering to enhance noise immunity and device protection.
Active Miller Clamp
An active clamp is often desirable to prevent unwanted dVDS/dt turn-on of power MOSFETs. Some gate drivers provide a clamp pin that is connected directly to the MOSFET gate. Internally, the pin is connected to a clamp switch connected to the lowest potential in the driver circuit. When the MOSFET is being turned off, the clamp switch is activated as the gate voltage falls below a certain level, about 2V, to ensure the MOSFET remains off throughout any ground bounce events or dVDS/dt transients. Figure 3 shows how the Miller clamp circuit is implemented in the STMicroelectronics STGAP1S driver .
Figure 3. The active Miller clamp clamps the gate to a low voltage after turn-off. Source STMicroelectronics AN4671 .
Under-Voltage Lockout (UVLO) disables the driver output temporarily at startup as the system power rails are energised, to protect the FET. A suitable threshold voltage for UVLO depends on the devices selected. To accommodate this, drivers such as the onsemi NCP51705 allow the threshold to be set using an external resistor.
Optimum Circuit Layout
Minimising parasitic effects such as trace inductance and resistances is also very important to ensure consistent switching performance. Using a gate-driver chip can bypass many of these challenges, and reduce correct circuit layout to a simple matter of ensuring the driver is placed as closely as possible to the MOSFET gate.
Controlling SiC MOSFETs at high switching speeds requires careful management of gate current and, ideally, asymmetrical gate-drive voltage (VGS) up to 15V to 20V for turn-on and -4V to -5V for turn-off. VGS of 0V may be acceptable in single-switch topologies, to save the extra complexity of generating a negative voltage for turn-off.
In any case, preventing spurious turn-on resulting from dVDS/dt transients or unintended gate currents is one of the most important aspects of designing the driver. A number of techniques can be considered, including optimising the MOSFET gate-source threshold voltage through device selection, applying negative turn-off voltage, managing the relationship between high-side/low-side turn-on/turn-off gate resistors, or clamping the gate to a low voltage to actively hold the MOSFET off.
Gate-driver ICs optimised for SiC applications are in the market now. These not only support various ways of preventing unwanted turn-off, but also incorporate important safety features like fast desaturation protection, which is difficult to design using discrete components.
 – STMicroelectronics AN4671. How to fine tune your SiC MOSFET gate driver to minimize losses.
 – onsemi TND6237/D, September 2017. SiC MOSFETs: Gate Drive Optimization.
 – Infineon AN2017-04. Advanced Gate Drive Options for Silicon-Carbide (SiC) MOSFETs using EiceDRIVER™.