Red Pitaya Anatomy 101Follow article
A look under the hood of the programmable test and measurement platform.
What makes the Red Pitaya stand out amongst other instruments is that it is designed to be a truly generic platform which can be configured for a diverse spectrum of uses through applications that are installed via the “Bazaar”, an online portal akin to a smartphone app store. This post explores how this is achieved with particularly flexible hardware and an open source software stack.
At the heart of the hardware platform is a Xilinx Zynq system-on-chip (SoC) that integrates a dual-core ARM processor, peripherals and FPGA into a single package. The ARM and peripherals are together termed the “processing system” (PS) and provide the computer that runs the O/S and application software. The system has 512MB RAM, Micro SD is used for storage and cards of up to 32GB are supported, and connectivity is via gigabit Ethernet and a USB UART debug interface.
The FPGA provides 28,000 cells of programmable logic along with RAM and DSP slices. This is used to interface the main ADCs and DACs, and also supports the implementation of hardware-based processing (for compute intensive functions), plus custom interfaces and expansion etc.
The Red Pitaya's high-speed digital converters provide two analogue inputs and two analogue outputs — all at 125MS/s and 14-bit resolution — and are connected to the PS via the FPGA and AXI bus. Above can be seen part of the ASCII art block diagram from the header of FPGA RTL top module file, which connects together the Zynq's external pins, PS and application modules.
An analogue extension connector provides four low-speed analogue inputs and four low-speed analogue outputs, each at 100kS/s and 12-bit resolution. A similar connector on the opposite side of the board provides digital expansion comprising of 16 FPGA GPIOs.
Daisy chaining boards is possible via two SATA connectors which each provide two differential pairs and support data rates of up to 500Mbps. Note that SATA drives are not supported and the connectors are simply used due to their performance and low cost cables being commonly available.
boot.bin: Contains the First Stage Bootloader, FPGA image and U-Boot bootloader;
uImage: Linux kernel;
devicetree.dtb: Linux device tree (describes peripherals etc);
uramdisk.image.gz: Initial ramdisk which contains the root file system.
Command line tools are also available and these can be executed remotely via SSH, enabling integration with things such as GNU Octave and Matlab, as well as being useful in testing and debugging. These are also Linux binaries and sit alongside the controllers in the software architecture, connecting to the FPGA and via this interfacing with the ADCs and DACs. Two such tools are currently provided, for signal generation and acquisition.
Part of the main.c file from the Oscilloscope application controller
The RedPitaya GitHub repository contains the source code for:
FPGA design sources (/FPGA/)
Linux kernel, U-boot, root filesystem (/OS/)
Nginx and controller module loader etc. (/Bazaar/)
Web applications (/Applications/)
Command line tools (/Test/)
Note that the OS sub-directory does not contain the full Linux and U-boot sources, which are cloned from elsewhere, and instead contains only platform-specific patches and config etc.
The FPGA bitstream can be generated using the WebPack (free-to-use) editions of Xilinx's ISE or Vivado design software. Rather than using the GUI, these are driven using a makefile-based build system that executes scripts and command line tools.
To be distributed via the Bazaar, applications must be given a unique Application ID and put in a single directory with that name, which is then packaged as a ZIP. In addition to the web app and controller, this must include an icon, and a JSON file with the name, description and version etc.
At present all applications use the same FPGA bitstream that is embedded in boot.bin and this will be sufficient for many new applications. However, it will also be possible to distribute custom bitstreams as part of applications, that implement modified and new FPGA-based DSP, and enable control of other instruments and interface with external peripherals via GPIO, for example.
For further details see the Developer Guide.
With its programmable logic the Zynq SoC provides a neat solution to integrating digital converters and implementing custom I/O along with hardware-based signal processing. Since it is highly configurable there may be something of a learning curve if you want to take advantage of its full capabilities when developing new applications. However, it's likely that many new apps will simply be able to use the existing FPGA designs as-is or with relatively minor modifications.
Built upon Linux and web technologies it is easy to imagine how the Red Pitaya could be customised and extended in a great many different ways. For example, for logging to a local or remote database, sending alarms via SNMP, or integrating with online services via public APIs.
Finally, the provided source code appears to be well structured and with plenty of comments and ASCII art diagrams, in addition to providing documentation on the wiki. All things which should hopefully make it easier for developers that are new to the platform to get up and running.