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PSoC 6 – an IoT Enhanced Powerhouse

Those who have read our previous posts will note that we have only had good things to say about the PSoC product line, be it a BLDC Motor kit or re-designing punched tape reader electronics, we’ve thoroughly enjoyed using PSoC ICs in the past.

When we were offered the chance to look at the PSoC6 CY8CKIT-062-BLE kit we jumped at it. We have been provided with an early access program (EAP) kit, but this will be very close to the standard kit that will available in the space of a few weeks from the time of writing. 

IoT Focus

Being the hottest topic around it shouldn’t be a surprise that IoT is the focus for the new PSoC range. That is not to say the PSoC6 would not suit other roles, but there are a few key adaptations that will differentiate it from previous incarnations that are aimed at IoT endpoint applications. Due to the flexibility of the PSoC family, these specialisations will almost certainly find other uses.

IoT Power

Power has two meanings for IoT endpoints:

  • The first is power as in Watts, having significant effects on the battery life of the product.
  • The second is power as in CPU speed, having a significant effect on the user experience.

These features are typically mutually exclusive and more CPU speed generally means more power use, so typically ends in a compromise of speed vs. power use.

A modern way of addressing this is adding a smaller CPU and while this sounds counter-intuitive, it’s becoming commonplace in many areas of CPU design. A popular example would be the new Samsung Exynos 9 (Galaxy Note 8 etc.) which uses the ARM big.little architecture, which allows the CPU to swap from high to low power CPUs on the fly as processing requirements change. 

The new PSoC 6 architecture aims to provide a third option — the equivalent of having your cake and eating it. The PSoC 62 has an ARM Cortex M4 with floating point and a second “low power” M0+. A point to note is the low power is in quotes for a reason: the M0+ is no slouch; this is the CPU in the PSoC 4 range which is more than enough for some applications on its own. Unlike the big.little, architecture both cores are available in parallel so can share workload, but just like the big.little, the system can turn off the high power CPU and run on the smaller lower power system when processing requirements are not required. By implementing the architecture in this way the PSoC 6 becomes a true multi-core CPU, all be it asymmetric.

IoT Security

Some would argue security is one of the biggest challenge areas in IoT to date. With data theft on the rise and barely a month going by without a big firm in the news for yet another breach, it’s something that could definitely be improved upon. The thought of a smart toothbrush telling the world of our brushing only for only 30 seconds and not a full minute may not sound scary, but IoT devices are not limited to toothbrushes; if your device had a microphone things could get a lot more serious!

Having in the past worked in set-top box design, where a large proportion of the software and hardware design is related to security and preventing ways of hacking. Breaches cost millions and so every effort was taken to ensure compromises were rare. The primary defence was to encrypt everything in both flash and RAM — at no point in a modern design should un-encrypted data surface. As you may imagine, this made CPUs for this purpose somewhat bespoke and secret to the NDA’th degree.

Moving on to 2017 and looking over the PSoC 6 architecture there are quite a few similarities to the CPUs of a previous life.

The PSoC 61, 62 and 63 architecture incorporates a cryptographic module to allow code to be secured so that it cannot be read (or booted) without the correct key. The CPU has one-time fuses so that this function can be “burned” into the chip, forcing a secure boot. This prevents any hacking of the device and malicious code being run. The quad SPI expansion port allows execute-in-place operation, which without a security cryptographic engine would fully circumvent any built-in security. For the PSoC 62 and 63 this has been thought of and there are cryptographic accelerators to make sure execute-in-place does not impact the trusted environment or performance.

The Kit CY8CKIT-062-BLE (-EAP in our case)

As with all Cypress CY8CKITs, it is well presented and comes with a magnetically closed storage box (with 4 neodymium magnets no less).

 

Inside the kit:

  • Instructions/Quickstart
  • USB-A USB-C cable
  • The PSoC BLE dev board itself (USB-C powered)
  • CY8CKIT-28-EPD 2.7 inch electronic paper display
  • CY5677 CySmart BLE 4.2 dongle
  • Assorted jumper wires

The PSoC BLE kit has both PMOD and Arduino shield connections to allow rapid prototyping and taking your Arduino project to the next level. If this is not enough just like the PSoC 4 kit (CY8CKIT-042-BLE), it comes with everything required to get started, including the equivalent of the kitchen sink — a Bluetooth dongle to ensure you can debug your device correctly. Your laptop may have Bluetooth, but it’s highly likely that it is not BLE capable and for this reason, Cypress provide a known working BLE device.

We have to be honest at this point and admit that our PSOC 4 kit has had less use than the supplied CY5677 CySmart BLE dongle, as it has proved to be a very handy debugging tool for any BLE device and not just Cypress devices!

BLE

We’ve previously discussed BLE with the Thunderboard article. For those who have missed the article, BLE is complicated and simple at the same time. It revolves around GATT profiles that act like a database for how data is to be transferred to and from the device. Sticking within these profiles makes implementation of a simple heart rate monitor a few hours work. Step outside the boundary of a GATT profile and you’ll need a lot more work. 

If you wish to learn more about BLE the PSoC4 kit came with excellent tutorials and these will still be relevant for the BLE aspects of PSoC6. 

USB-C powered

USB-C can be a problem child when it comes to compatibility, especially PD (Power Delivery). Without going into too much detail there are many many configurations and standards applicable to USB-C PD1, PD2 and now PD3. This is before we get to transfer of data and the requirements for high-speed switching or AUX modes…. 

All of this boils down to requiring a rock solid PD controller and the Cypress kit comes with a CYPD3126, part of the CCG3 family of Power Delivery ICs, which are fully featured (PD3 and even billboard support (AUX mode)). If it performs like the CCG2 we expect only good things.

PSoC is special

If you read either the BLDC or recent tape punch article, you will know PSoC is not just any micro — it’s a FPGA/CPLD and analogue front-end to boot. PSoC6 has variants will all of the goodies PSoC 4 and 5 support, and the high-end devices, and as such are seriously powerful. For digital designs the UDB (internal FPGA) allowing significant component reduction. Need another timer or shift register, no problem!

The integrated analogue fabric does the same for the analogue domain. It’s quite possible to have almost no other hardware for many designs. This includes cap touch or other such analogue domain problems.

Applying power

As can be seen in the video, the device comes pre-programmed with one of the demos. In the demo, both touch and E-ink are enabled, and as with all Cypress kits, all source code is provided.

By installing the kit files and the latest PSoC creator, we can open the demos and have a quick look under the hood.

Opening the E-INK demo should look familiar to those who have previously used PSoC Creator, as we used it the PSoC BLDC kit example

Browsing the code we quickly found the source files. There are separate files for everything, which makes re-using the code much easier.

/* Header file includes */
#include <project.h>
#include "touch.h"
#include "screen.h"

/*******************************************************************************
* Function Name: int main()
********************************************************************************
*
* Summary: 
*  Main function that continuously reads touch information and updates the screen
*  accordingly
*
* Parameters:
*  None
*
* Return:
*  int
*
* Side Effects:
*  None  
*
*******************************************************************************/
int main(void)
{
    /* Variable used to store the touch information */
    touch_data_t touchData;

    /* Enable global interrupts */
    __enable_irq();

    /* Initialize the display, touch detection and low power modules */
    InitScreen();
    InitTouch();

    for (;;)
    {
        /* Read the touch information from the CapSense buttons and the slider */
        touchData = GetTouch();

        /* Update the screen according to the touch input */
        UpdateScreen(touchData);
    }
}

/* [] END OF FILE */

cm0p_code

/* Header file includes*/
#include <project.h>

/*******************************************************************************
* Function Name: int main()
********************************************************************************
*
* Summary: 
*  Empty function : Code execution will not happen as the Cortex-M4 is not enabled
   by the Cortex-M0+ in this project.
*
* Parameters:
*  None
*
* Return:
*  int
*
* Side Effects:
*  None  
*
*******************************************************************************/
int main(void)
{
}

/* [] END OF FILE */

cm4_code

Unlike previous PSoC examples, there are two “main” files: a main_cm4 and main_cm0p. These are the two cores the M4 and M0+. For the example we opened, all code was executing in the cm0p file, so the M4 was inactive. Another example of the power of the M0+ in its own right, the PSoC6 products are aimed at serious high demand applications where typical CPUs would struggle.

/* Array that stores the text pages */   
char const textPage [TOTAL_TEXT_PAGES][TEXT_PAGE_CHARACTER_SIZE] =
{   
    /* Pages of "PSoC 6 MCU FEATURES" menu item */
    /* Page 1 */
    { 
    "PSoC 6 MCU FEATURES (Page 1 of 8)"\
    "                                 "\
    "CPU Subsystem:                   "\
    "150-MHz ARM Cortex-M4 CPU with   "\
    "single-cycle multiply (Floating  "\
    "Point and Memory Protection Unit)"\
    "                                 "\
    "100-MHz Cortex M0+ CPU           "\
    "                                 "\
    "Two DMA controllers with sixteen "\
    "channels each                    "\
    "                                 "\
    },
    
    /* Page 2 */
    { 
    "PSoC 6 MCU FEATURES (Page 2 of 8)"\

etc...

Looking in the screen_contents.c file we can see the E-INK display files including the Cypress artwork. 

An interesting point to call out is with the correct set-up of the compiler the use of the “const” will equate to this data being stored in flash and not using up the static ram, which is important when you only have 512k of RAM in the smaller parts.

Final words

As usual, the example files are a great start for any project. With the dual processor architecture of PSoC 6 it’s quite possibly the only chip required for a full IoT solution: security, BLE, analogue or digital, it has it all. The CY8CKIT-62-BLE is one of the more fully featured kits to date and will be very useful in the future.

Karl is a design engineer with over a decade of experience in high speed digital design and technical project leadership in the commercial electronics sector.

Comments

0 Votes
lgarnand

October 25, 2017 09:57

54 pounds and change or $75 US when it becomes available (which will be soon). There are other low cost boards in the works that will be similar to the $10 PSOC 5, and the $10 and $4 PSOC 4 boards that are so popular.

0 Votes
syates1965

October 25, 2017 09:58

Price??

davecole

October 25, 2017 09:57

@syates1965 The price of the Cypress PSOC6 is displayed at the top of the page on the right hand side. TIP: If you are logged in it will show you local pricing.