Implement a simple digital circuit through FPGA trainer board and in Xilinx Vivado IDE (Verilog)Follow project
|1||Digilent 410-183 Basys Artix-7 Development Board||134-6451|
After completing this lab, you will be able to:
- Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA device located on the Basys3 board
- Use the provided Xilinx Design Constraint (XDC) file to constrain the pin locations
- Simulate the design using the Vivado simulator
- Synthesize and implement the design
- Generate the bitstream
- Configure the FPGA using the generated bitstream and verify the functionality
This lab is broken into steps that consist of general overview statements providing information on the detailed instructions that follow. Follow these detailed instructions to progress through lab1.
The design consists of some inputs directly connected to the corresponding output LEDs. Other inputs are logically operated on before the results are output on the remaining LEDs as shown in Figure 1.
Figure 1. The Completed Design
Step 1: Create a Vivado Project using IDE
Step 2: Simulate the Design using Vivado Simulator
Step 3: Synthesize the Design
Step 4: Implement the Design
Step 5: Perform the Timing Simulation
Step 6: Verify Functionality in Hardware
Create a Vivado Project using IDE (Step 1)
Launch Vivado and create a project targeting the XC7A35TCPG236-1 (Basys3) and using the vL HDL. Use the provided lab1.v and lab1.xdc files from the 2020_1_artix7_sources\lab1
Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2020.1> Vivado 2020.1
Click Create New Project to start the wizard. You will see Create A New Vivado Project dialog box. Click Next.
Click the Browse button of the Project location field of the New Project form, browse to C:/Digilent/Basys3Workshop/2020_1_artix7_labs, and click Select.
Enter lab1 in the Project name Make sure that the Create Project Subdirectory box is checked. Click Next.
Figure 2. Project Name and Location entry
Select RTL Project option in the Project Type Make sure that the Do not specify sources at this time box is unchecked. Click Next.
Using the drop-down buttons, select verilog as the Target Language and Mixed Simulator Language in the Add Sources
Figure 3. Selecting Target and Simulator language
Click on the Add Files button, browse to the Downloads folder, select lab1.v, click OK. Make sure that the Copy sources into project box is checked. Click Next to get to the Add Constraints form.
The constraint file lab1_basys3.xdc and lab1_nexys4.xdc are automatically added. Highlight and delete the XDC file not for the target board by clicking on the “X” on the right-hand side of the window. Make sure that the Copy constrains files into project box is checked.
If no files are added, click on the Add Files… button, browse to the Downloads folder (if necessary), select lab1_basys3.xdc or lab1_nexys4.xdc and click OK (if necessary), and then click Next.
This Xilinx Design Constraints file assigns the physical IO locations on FPGA to the switches and LEDs located on the board. This information can be obtained either through the board’s schematic or the board’s user guide.
In the Default Part form, using the Parts option and various drop-down fields of the Filter If using the Basys3 board, select the XC7A35TCPG236-1. Click Next.
Figure 4. Part Selection for the Basys3
You can select the Boards Specify option, select Artix-7 under the Library filter, and select the appropriate board. Notice that Nexys4 and the Basys3 are not listed as they are not in the tool's database.
Click Finish to create the Vivado project.
Use the Windows Explorer and look at the C:\Digilent\Basys3Workshop\2020_1_artix7_labs\lab1 directory. You will find that lab1.cache and lab1.srcs directories and the lab1.xpr (Vivado) project file has been created. The lab1.cache directory is a placeholder for the Vivado program database. Two directories, constrs_1 and sources_1, are created under lab1.srcs directory; deep down under them, the copied lab1.xdc (constraint) and lab1.v (source) files respectively are placed.
Figure 5. Generated directory
Open lab1.design source and analyze the content.
In the Sources pane, double-click lab1.design source entry to open the file in text mode.
Figure 6. Opening the source file
`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////// // Entity Name: lab1 //////////////////////////////////////////////////////////////////////// module lab1( input [7:0] swt, output [7:0] led ); wire [7:0]intled; assign intled = !swt; assign intled = swt & !swt; assign intled = swt & swt; assign intled = intled | intled; assign intled[7:4] = swt[7:4]; assign led = intled; endmodule
In the VERILOG code, lines 2-4 are comment lines describing the entity name and the purpose of the module.
Lines 6-9 declare the module called lab1 and define the port interface signals. Two vectors are used, 8 signals each: inputs swt (switches) and outputs led.
Line 10 declares a wire used to connect gates or modules for creating the LED state.
Lines 11-15 describe the functionality, while line 16 assigns computed values to the output signals led.
Line 17 closes the module.
Open the lab1_basys3.xdc source and analyze the content.
In the Sources pane, expand the Constraints folder and double-click lab1.xdc entry to open the file in text mode.
Figure 7. Opening the constraint file
Lines 5-20 define the pin locations of the input switches [7:0] and lines 25-40 define the pin locations of the output LEDs [7:0].
Perform RTL(register-transfer level ) analysis on the source file.
Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and click on Schematic.
The model (design) will be elaborated and a logic view of the design is displayed.
Figure 8. A logic view of the design
Notice that some of the switch inputs go through gates before being output to LEDs and the rest go straight through to LEDs as modelled in the file.
Simulate the Design using the Vivado Simulator Step 2
Add the lab1_tb.design source testbench file.
Click Add Sources under the Project Manager tasks of the Flow Navigator pane.
Figure 9. Add Sources
Select the Add or Create Simulation Sources option and click Next.
Figure 10. Selecting Simulation Sources option
In the Add Sources Files form, click the Add Files… button. Browse to the c:\Digilent/Basys3Workshop/2020_1_artix7_sources/lab1 folder and select lab1_tb.v and click OK.
Make sure that the Copy sources into project box is checked. Click Finish. Select the Sources tab and expand the Simulation Sources group. The lab1_tb.v file is added under the Simulation Sources group, and lab1.v is automatically placed in its hierarchy as a dut (device under test) instance.
Figure 11. Simulation Sources hierarchy
Using Windows Explorer, verify that the sim_1 directory is created at the same level as constrs_1 and sources_1 directories under lab1.srcs directory, and that a copy of lab1_tb.v is placed under lab1.srcs > sim_1 > imports > lab1. Double-click on the lab1_tb in the Sources pane to view its contents.
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// //Entity Name: lab1_tb ////////////////////////////////////////////////////////////////////////////////// module lab1_tb(); wire [7:0] leds; reg [7:0] switches, e_leds; function [7:0] exp_led; input [7:0]swt; begin exp_led = !swt; // exp_led = swt; // coment the previous line and after uncomment this line // // this line is use to set a fail in testbench. // // at the line 33 the output in Tcl console will show the output for // // led and teh output expected exp_led = swt & !swt; exp_led = swt & swt; exp_led = exp_led | exp_led; exp_led[7:4] = swt[7:4]; end endfunction lab1 DUT(.swt(switches), .led(leds)); integer i; initial begin $monitor(leds, switches, e_leds); for (i=0;i<255;i=i+1) begin #50 switches = i[7:0]; #10 e_leds = exp_led(switches); if (e_leds == leds) $display("LED output matched at %0t", $time); else $display("LED output mis-matched at %0t : expected: %b, actual: %b", $time, e_leds, leds); end end endmoduleFigure 13. The self-checking testbench
Figure 12. The self-checking testbench
The module is void for a testbench (there is no input or output signal for test).
The architecture declarations are:
- The tested component DUT (device under test)
- Some wires and reg
- A function describing the same module functionality for the expected value computation
The architecture body:
- instantiates the DUT (device/module under test).
- define the stimuli generation, and compare the expected output with what the DUT provides.
- print the message in the simulator console window when the simulation is run.
Simulate the design for 200 ns using the Vivado simulator.
Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane.
A Project Settings form will appear showing the Simulation properties form.
Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click OK.
Figure 13. Setting simulation run time
Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator pane.
The testbench and source files will be compiled and the Vivado simulator will be run (assuming no errors). You will see a simulator output similar to the one shown below.
Figure 14. Simulator output
You will see four main views: (i) Scopes, where the testbench hierarchy, as well as glbl instances, are displayed, (ii) Objects, where top-level signals are displayed, (iii) the waveform window, and (iv) Tcl Console where the simulation activities are displayed. Notice that since the testbench used is self-checking, the results are displayed as the simulation is run.
Notice that lab1.sim directory is created under the lab1 directory, along with several lower-level directories.
Figure 15. Directory structure after running behavioural simulation
You will see several buttons above to the waveform window which can be used for the specific purpose as listed in the table below.
Table 1: Various buttons available to view the waveform
Click on the Zoom Fit button ( ) to see the entire waveform.
Notice that the output changes when the input changes.
You can also float the simulation waveform window by clicking on the Float button on the upper right-hand side of the view. This will allow you to have a wider window to view the simulation waveforms. To reintegrate the floating window back into the GUI, simply click on the Dock Window button.
Figure 16. Float Button
Figure 17. Dock Window Button
Change display format if desired.
Select switches[7:0] in the waveform window, right-click, select Radix, and then select Hexadecimal. Leave the leds[7:0] and e_led[7:0] radix to binary as we want to see each output bit.
Add more signals to monitor the lower-level signals and continue to run the simulation for 500 ns.
Expand the lab1_tb instance, if necessary, in the Scopes window and select the dut instance. The swt[7:0] and led[7:0] signals will be displayed in the Objects window.
Figure 18. Selecting lower-level signals
Select swt[7:0] and led[7:0] and drag them into the waveform window to monitor those lower-level signals.
On the simulator tool buttons ribbon bar, type 500 over in the simulation run time field, click on the drop-down button of the units field, and select ns ( ) if we want to run for 500 ns (total of 700 ns), and click on the ( ) button. The simulation will run for an additional 500 ns.
Click on the Zoom Fit button and observe the output.
Figure 19. Running simulation for additional 500 ns
Observe the Tcl Console and see the output is being displayed as the testbench uses the report task.
Figure 20. Tcl Console output after running the simulation for additional 500 ns
Close the simulator by selecting File > Close Simulation. Click OK and then click No to close it without saving the waveform.
Uncomment line 13 and comment the line 12 to fail the simulation test
Using Windows Explorer, comment the line 12 and uncomment line 13 after that save the file and click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator panel.
Figure 22. Simulator output after 200ns
Notice that since the testbench used is self-checking, the results are displayed as the simulation is run. Observe the Tcl Console and see the output is being displayed as the testbench uses the report task.
Figure 23. Tcl console output
In Tcl console, it is shown at with point in time the signals are mismatched, for example at 60ns the test bench will show automatically the expected signal (00000000) and the actual signal (00000001).
Synthesize the Design (Step 3)
Synthesize the design with the Vivado synthesis tool and analyze the Project Summary output.
Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane.
The synthesis process will be run on lab1.v file (and all its hierarchical files if they exist). When the process is completed a Synthesis Completed dialog box with three options will be displayed.
Select the Open Synthesized Design option and click OK as we want to look at the synthesis output before progressing to the implementation stage.
Click Yes to close the elaborated design if the dialog box is displayed.
Select the Project Summary tab and understand the various windows.
If you don’t see the Project Summary tab then select Layout > Default Layout, or click the Project Summary icon.
Figure 21. Project Summary view
Click on the various links to see what information they provide and which allows you to change the synthesis settings.
Click on the Table tab in the Project Summary tab.
Notice that there are an estimated three LUTs and 16 IOs (8 input and 8 output) that are used.
Figure 22. Resource utilization estimation summary for the Basys3
In The Flow Navigator, under Synthesis (expand Synthesized Design if necessary), click on Schematic to view the synthesized design in a schematic view.
Figure 23. Synthesized design’s schematic view
Notice that IBUFs and OBUFs are automatically instantiated (added) to the design as the input and output are buffered. The logical gates are implemented in LUTs (1 input is listed as LUT1, 2 input is listed as LUT2, and 3 input is listed as LUT3). Four gates in RTL analysis output are mapped onto four LUTs in the synthesized output.
Using Windows Explorer, verify that lab1.runs directory is created under lab1. Under the runs directory, synth_1 directory is created which holds several files related to synthesis.
Figure 24. Directory structure after synthesizing the design
Implement the Design (Step 4)
Implement the design with the Vivado Implementation Defaults (Vivado Implementation 2020) settings and analyze the Project Summary output.
Click on Run Implementation under the Implementation tasks of the Flow Navigator pane.
The implementation process will be run on the synthesized design. When the process is completed an Implementation Completed dialog box with three options will be displayed.
Select Open implemented design and click OK as we want to look at the implemented design in a Device view tab.
Click Yes, if prompted, to close the synthesized design.
The implemented design will be opened.
In the Netlist pane, select one of the nets (e.g. led_OBUF) and notice that the net is displayed in the X1Y1 clock region in the Device view tab (you may have to zoom in to see it).
If it is not selected, click the Routing Resources icon to show routing resources.
Figure 25. Selecting a net
Figure 26. Viewing implemented design for the Basys3
Close the implemented design view and select the Project Summary tab (you may have to change to the Default Layout view) and observe the results.
Select the Post-Implementation tab.
Notice that the actual resource utilization is three LUTs and 16 IOs. Also, it indicates that no timing constraints were defined for this design (since the design is combinatorial).
Figure 27. Implementation results for the Basys3
Using Windows Explorer, verify that impl_1 directory is created at the same level as synth_1 under lab1.runs directory. The impl_1 directory contains several files including the implementation report files.
In Vivado, select the Reports tab in the bottom panel (if not visible, click Window in the menu bar and select Reports), and double-click on the Utilization Report entry under the Place Design section. The report will be displayed in the auxiliary view pane showing resource utilization. Note that since the design is combinatorial no registers are used.
Figure 28. Available reports to view
Perform Timing Simulation (Step 5)
Run a timing simulation.
Select Run Simulation > Run Post-Implementation Timing Simulation process under the Simulation tasks of the Flow Navigator pane.
The Vivado simulator will be launched using the implemented design and lab1_tb as the top-level module.
Using Windows Explorer, verify that the timing directory is created under lab1.sim > sim_1 > impl directory. The timing directory contains generated files to run the timing simulation.
Click on the Zoom Fit button to see the waveform window from 0 to 200 ns.
Right-click at 50 ns (where the switch input is set to 0000000b) and select Markers > Add Marker.
Similarly, right-click and add a marker at around 55.000 ns where the leds change.
You can also add a marker by clicking on the Add Marker button (). Click on the Add Marker button and left-click at around 60 ns where e_led changes.
Figure 29. Timing simulation output
Notice that we monitored the expected led output at 10 ns after the input is changed (see the testbench) whereas the actual delay is about 5.000 ns.
Close the simulator by selecting File > Close Simulation without saving any changes.
Generate the Bitstream and Verify Functionality (Step 6)
Connect the board and power it ON. Generate the bitstream, open a hardware session, and program the FPGA.
Make sure that the Micro-USB cable is connected to the JTAG PROG connector (next to the power supply connector).
Make sure that the board is set to use USB power (via the Power Select jumper JP2 on the Basys3)
Figure 30. Board connection for the Basys3
Power ON the board.
Click on the Generate Bitstream entry under the Program and Debug tasks of the Flow Navigator pane.
The bitstream generation process will be run on the implemented design. When the process is completed a Bitstream Generation Completed dialog box with two options will be displayed.
Figure 31. Bitstream generation
This process will have generated a lab1.bit file under impl_1 directory in the lab1.runs directory.
Select the Open Hardware Manager option and click OK.
The Hardware Manager window will open indicating “unconnected” status.
Click on the Open target link.
Figure 32. Opening new hardware target
Click Auto Connect and wait for Vivado to find and connect.
The Hardware Session status changes from Unconnected to the server name and the device is highlighted. Also, notice that the Status indicates that it is not programmed.
Figure 33. Opened hardware session for the Basys3
Click on the Program link in the green information bar to program the target FPGA device.
Another way is to right-click on the device and select Program Device…
Figure 34. Selecting to program the FPGA
Click Program to program the FPGA.
The DONE light will light when the device is programmed. You may see some other LEDs lit depending on switch positions.
Verify the functionality by flipping switches and observing the output on the LEDs (Refer to the earlier logic diagram).
When satisfied, power OFF the board.
Close the hardware session by selecting File > Close Hardware Manager.
Click OK to close the session.
Close the Vivado program by selecting File > Exit and click OK.
The Vivado software tool can be used to perform a complete design flow. The project was created using the supplied source files (HDL model and user constraint file). A behavioural simulation using the provided testbench was done to verify the model functionality. The model was then synthesized, implemented, and a bitstream was generated. The timing simulation was run on the implemented design using the same testbench. The functionality was verified in hardware using the generated bitstream.