How does Via stitching and area fill work in DSPCB?

Background Information.

This feature replicates the placing of vias just as would do manually one at a time, but as a complete area.

This means that say a GND area of vias cannot pass through another net such as a 3v3 net area on a different layer, the placement of vias will be blocked. If the area is the same net such as GND in this case, the vias will be placed as holes, but without thermal relief. In all cases, the areas of copper pour on other layers, clear the pour area(s) first before using Apply Vias and re-pour the areas afterwards to have thermal relief or clearances produced.

A further detail to be aware of is, that if the selected shape that you wish to Apply Vias to is a copper pour area, this must be poured! The reason for this is a pour area added to the PCB only shows the boundary for the calculated pour to fill. It also automatically defines the net to be used. To get thermal relief around the vias on this poured area you need to clear the copper pour and re-pour. A final point regarding the copper pour area is that this is filled with multiple copper ‘tracks’ to fill the area defined, filling copper around all the pads, vias and shapes. It does not have a specific “shape”, the Apply Vias option cannot have the “On the Shape” option applied.

Using Apply Vias.

Now you understand the background of how this feature operates we now examine the options and how to apply to your designs.

This feature/tool is “Apply Vias” is available from the menu [Utilities][Apply Vias] and opens the following Form for the selected Copper Shape.

The following provides a comprehensive description of the options available in the  “Vias Placed” action/mode selected.

For a PCB track the appropriate “Vias Placed” modes are:

For a copper area all four modes are available. The exception is copper pour area which does not support “On the shape” as it does not have a defined shape.

The options available on the form are shown here and discussed below.

Around outside means placing vias in all possible legal positions around the outside of the selected shape and on the net given. This can be used for shielding a track or other item. It was added specifically to support the requirements of an advanced designer. It can be applied around a track on an inner layer with copper areas above and below to provide advanced screening.

On the shape means along an open shape, such as a track, or along the edge of a closed shape. This could be used to stapling an item to a power plane or two power tracks for improved current sharing. Note this is not applicable to a copper pour area.

Example a power track on top and bottom layers stapled/stitched together:

Example applied to a copper shape or copper pour area:

Around inside means inside the edge of a closed shape.

Fill the shape means covering the interior of a closed shape with vias.

Real Application Example.

A typical design will probably have multiple layers with many tracks and components, these will all be avoided by “Apply Vias”.

Using the supplied RaspPi PSU as an example, this has two layers and large ground copper pour areas on the top and bottom layers:

Selecting a pour area on the top copper layer and using “Apply Vias – Fill the Shape” we get the following result obeying the Design Rules – Spacing settings illustrating the placement of the vias.

However as the copper pour is present the drill holes will be drilled through the copper area, no thermal break or spokes are produced. 

If thermal breaks are required, clear the copper pour and re-pour.
Note: Clearing all copper pour areas and re-pouring is always advised for all DSPCB designs before manufacturing.

IMPORTANT!

Your design may consist of copper areas, copper pours and power planes on many layers as illustrated below.

Here we have:

Top Copper: A closed copper shape assigned to GND

Layer 2: A poured shape assigned to net 3V3.

Power planes: Assigned to GND and 3V3

Layer 5: With a closed copper shape assigned to 3V3 and poured shape assigned to GND.

Bottom Copper: A closed copper shape assigned to GND.

A quick diversion to show what NOT to do!
Here we have all the pour areas ‘poured’ and selected the GND copper area on the Top Copper layer and ‘fill the shape’.

The result is as shown, the poured area on layer 2 which is on net 3V3 has correctly blocked any via placement in this area.

You must clear the poured areas BEFORE using “Apply Vias”.

With the pour areas cleared and the Top Copper area select to apply vias:

We now have the expected via coverage of the area.

All that remains is to pour the copper:

You may notice 3 ‘missing’ columns of vias in the above image, this is correct as there is a “Spacing Rule” in the design technology for via to shape which has been obeyed.

Looking at the layers they will have thermal breaks and spokes on a copper pour area of the same net. No thermal breaks on a copper area and clearance as specified for the via if passing through a different net, here are two example layers:

There are a few other options to mention:

Random, varies the spacing of the vias around the nominal set spacing value. This can be useful for reducing standing waves/resonances in circuits that contain high frequency harmonics. This can be applied to tracks:

and copper areas:

Staggered, is an alternative “Fill the shape” option for copper areas. 

Save Settings, will save the current settings, and use them to prime the dialog, where appropriate, the next time it is used.

With many options available you can select the options as you require to meet your design requirements.