HDMI I/O Video-Processing System on the Artix-7 FPGA I - HardwareFollow article
Adam Taylor is bringing a new perspective to FPGA projects with his recent use of the Artix-7 XC7A200T FPGA to implement an embedded vision concept. His popular blog series, the MicroZed Chronicles, begins by taking a look at the hardware chosen for a simple HDMI input-and-output video-processing system. When searching for hardware to execute this project, Taylor describes his choice to use the Nexys Video Artix-7 FPGA Trainer Board due to its I/O and peripheral interfaces. These interfaces, Taylor says, “are intended for prototyping video and vision applications… [and] designed to support video reception, processing, and generation/output.”
Using VHDL with an RTL approach, Taylor provides an outline of the image-processing pipeline architecture pictured below. The supervising processor, a MicroBlaze soft-core RISC, monitors communications with the user interface and configures the image-processing pipeline. In order to create his own image-processing functions, Taylor lists the necessary peripherals for the MicroBlaze processor to support as follows:
- AXI UART – Enables communication and control of the system
- AXI Timer – Enables the MicroBlaze to time events
- MicroBlaze Debugging Module – Enables the debugging of the MicroBlaze
- MicroBlaze Local Memory – Connected to DLMB and ILMB (Data & Instruction Local Memory Bus)
Taylor then goes on to describe the chosen data processing format for this simple project architecture. By converting data received from the HDMI input to an AXI Streaming (AXIS) format, he uses the Vivado Design Suite and several of its provided image-processing IP blocks. The required IP blocks to create this simple image-processing pipeline are then listed alongside information on where readers can find them.
The video-processing chain is centered on the VDMA, which is used to move the image into the DDR memory. A memory interface generator is used to create this DDR interface to the Nexys Video’s SDRAM, thus constructing a common frame store accessible using the AXI interconnect. This is illustrated in the diagram provided below, which shows the IP block conversion from streamed data to memory-mapped data for read and write channels.
The article is concluded with the initial base system in Vivado displaying the Nexys Video HDMI example. You can find the original article here before Taylor’s upcoming article, which will chronicle the required software configuration for this image-processing pipeline.