Fast SPI connections through isolation
Isolating SPI is very simple in the most cases. The lines are all unidirectional and use standard digital logic levels for data, and no open collector outputs to support wire and connections. As long as the speed is fairly modest, below about 5MHz clock rates, most digital isolators will do the job with no further fuss. Unfortunately as the clock rate increases there is a catch that limits the speed.
Standard implementations of SPI use the clock signal, SCLKM, generated by the Master device to control all movement of data on the bus. Data moves between the Master and Slave as if they were two interconnected shift registers. The Master and Slave present data to the bus on one phase of the clock and read the data into their shift register on the opposite phase. This system works fine as long as the round trip propagation delay through the bus is less than half of the clock period, because the data must be back to the master by the next clock edge, half a clock period later.
Incorporating isolation into an SPI bus constrains the SCLKM rate because data from the Slave device must arrive at the Master before the next clock edge. Since the minimum time required for this to happen is 2x the maximum propagation delay, this sets a maximum limit on the clock rate.
We usually recommend the ADuM1401C for this job since it has a guaranteed speed of 45 MHz with a maximum propagation delay of 32 ns. When used to isolate SPI, the clock half period must be greater than 2 propagation delays, or a maximum SCLKM rate of 7.8MHz. This is a severe limitation on the data rate compared to the maximum throughput of the digital isolator. In fact, a digital isolator would need a maximum guaranteed propagation delay less than 5.5 ns to support 45 MHz SPI.
Luckily there is a straightforward solution to eliminate this bottleneck. If the SCLKM signal is wrapped back through the coupler along with the data from the Slave device, the timing between the new signal, SCLKS, and the data is the same to within the propagation delay skew of the coupler. SCLKS can be used to clock data back into the Master at rates which are again set by guaranteed data rate of the coupler. After each transaction, the secondary buffer MREG2 is copied into MREG1 In this example, that raises the SPI clock rate to the full 45MHZ, a 5x improvement. The cost of this solution is the additional coupler channel to wrap the Master clock signal and an extra input shift register in the master controller
The recommended iCoupler devices for SPI applications are the ADuM1401C and ADuM3441. Data rates of up to 50 MHz can be achieved with these devices.
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To get rid of that problem, I have to delete the component in the crashed schematic and add it again (with renaming) and connect all the wires again. Since this is the third time DS crashed and I have to connect several (>20 Wires) again, I am annoyed doing that to get a clean version of my schematics.
Why has every schematic its own component bin? Is there a good argument for that or is it only a relict of upgrading older versions?
The first issue has a bad work around but I still have the problem with the destroyed schematic (which is in fact the reason of the issue above).
I'm using DS4 since one Month now and think this is a nice tool (especially for hobby users like me). BUT:
The software crashed sometimes and this caused my multi-sheet schematic to get out of order. Since the components should be spread along the sheets, I use the component bin very often.
First problem is that after the crash, my schematic which was last edited is now empty and black - no components, nothing.
Second problem is when I am using the back up file the component bin is not right. This means that I have an instance in sheet1 named "XYZa" (gate a of XYZ) and in the sheet2 "XYZb" (gate b of XYZ) but in sheet1 the component bin reports the that XYZb is still "available".
Is there something (e.g. a tool) that can repair the component bin or the content?
Maybe this could be an improvement for laterversions, that there is only one component bin for the whole project. Placing one gate of an instance will add the missing gates for all schematics in the project. No new adding, renaming of components.
There is a third error I have noticed: When creating a new schematic and trying to copy content (gates of components and some components) from an old schematic to this new one the gates can not be copied due to this "adding and renaming" of components. This nearly destroyed my hole design while I tried to get some order in my design (spliting in power, analog and digital) because I cut the gate and components around it and I could not paste it again but the schematics where saved due to the removement of the gate (in conjungtion with the component bin).
Is there any suggestion to that issue? If you need some more details, please let me know.
Thanks in advance.
P.S.: It is the same with DS5