Enhanced XILINX FPGA and SoC Debug and Programming capability from Digilent JTAG Cables.
While Digilent builds this functionality directly into their Xilinx FPGA boards like the ZYBO and ARTY platforms (See RS https://uk.rs-online.com/web/c/semiconductors/semiconductor-development-kits/programmable-logic-development-kits/?applied-dimensions=4291935200) their JTAG-HS programming cables have been released to augment other Xilinx boards, by providing high-speed programming/debugging tools for Xilinx FPGAs and SoCs. Fully compatible will all Xilinx Tools, they can be seamlessly driven from iMPACT, ChipScope™, EDK, and Vivado™.
Powered via Host PC micro USB 2.0 port that will recognize it as a Digilent programming cable even before a target board is attached. The HS3 attaches to target boards using Xilinx’s 2x7, 2mm programming header, while the HS2 version supports both 6 and 14 (2x7) pin connector interfaces.
The cables feature a separate Vref pin to supply the JTAG signal buffers and drive target boards with signal voltages from 1.8V to 5V and user settable bus speeds up to 30MBit/sec via 24mA three-state buffers. To function correctly, the HS3’s Vref pin must be tied to the same voltage supply (VCCO_0) that drives the JTAG port on the FPGA.
JTAG-HS2 FPGA Programming Cable is IEEE 1149.7-2009 Class T0 - Class T4 (includes 2-Wire JTAG) compatible, and usable with all Xilinx tools as well as fully supported by Digilent's Adept software and Adept SDK, the JTAG/SPI frequency settable by user with programming modes 0/2 up to 30Mbit/sec, modes 1/3 up to 2Mbit/sec.
One quirk of the XILINX FPGA is that it periodically need reset during programming. To handle this the cable supports with an Open-drain buffer on pin 14 allows processor reset of Xilinx Zynq platform.
RS Stock Numbers
Digilent JTAG cable was recently featured in Adam Taylors MicroZed Chronicles which is an excellent and insightful series of practical articles to learn about FPGAs. http://adiuvoengineering.com/?page_id=285
An FPGA is a semiconductor matrix of Configurable Logic Blocks that can be configured and connected together by programming SRAM, as logic gates, a processor, or a block of RAM). The device can be updated or changed in use after production.
Digilent JTAG Programming cable supported Target Devices
- Xilinx FPGAs
• Xilinx Zynq-7000
• Xilinx CoolRunner™/CoolRunner-II CPLDs
• Xilinx Platform Flash ISP configuration PROMs
• Selected third-party SPI PROMs
• Selected third-party BPI PROMs
Target Devices Not Supported
- Xilinx 9500/9500XL CPLDs
• Xilinx 1700 and 18V00 ISP configuration PROMs
• Xilinx FPGA eFUSE programming