A new challenge emerges for wearable and IoT applications
We all know software integration, connectivity, RF design and security drive a large part of the design cycle within IoT applications. The one challenge that has remained consistent throughout the industry over time is power consumption.
While engineers are no strangers to low power design, the requirements of next generation of portable, roamable and battery-operated applications in wearables and IoT has revealed a trend.
Microcontrollers and RF chipsets running on low energy sources require quartz crystals optimized specifically for the IoT. Next generation crystals address the emerging challenge with new manufacturing and design techniques specifically aimed at lowering the plating capacitance (CL) and the equivalent series resistance (ESR) inherent within every quartz resonator.
Why are a lower CL and ESR an emerging challenge? First, CL and ESR are mutually exclusive optimization parameters requiring quartz technology to leap forward. In general, a lower CL or a lower ESR can be easily attained. However, both parameters decreasing simultaneously while maintaining excellent yield is a real engineering and manufacturing challenge. Moreover, ESR can vary greatly over temperature. Maintaining a low ESR at 105C or 125C is especially challenging.
While quartz design and construction are challenging, the true challenge is presented at the applications level. The reason is very simple: While previous generations of quartz technology address CL requirements between 8pF and 12.5pF, new crystals must reach 6pF, 4pF or 3pF in order to run reliably with energy-saving silicon. The application benefits from power conservation. However, any engineer will notice that 3pF is similar in magnitude to the parasitic capacitance of PCB traces and the input of most MCU pins. The result is a stronger dependence on the variation of those parasitic capacitances.
Abracon’s W-Series quartz crystals offer low ESR specifications in combination with low CL options to address the energy-saving MCU & portable communication chipset market trends. It’s the most comprehensive series on the market with the lowest CL and lowest ESR available.
The Design Risk
In the past, it was never necessary to account for every pF on the PCB. Small variations would lead to 5ppm or 10ppm offsets and would only marginally affect the operating point of the oscillator circuit. With such low capacitances, the design risk increases. More considerations are necessary in order to maintain a healthy safety factor of oscillation across all corners. Using a crystal with a guaranteed low ESR is one part of the equation, but careful design and in-system validation are also helpful.
While the sensitivity to PCB capacitance in low-energy systems using low CL plated crystals may be higher, it has become a necessary part of oscillator design. This emerging challenge has to be addressed carefully since the entire board rests on the functionality, safety factor and long-term reliability of the crystal oscillator.
The attached application note addresses why these new considerations have become important and how to analyze your oscillator mating to a low-energy MCU or RF chipset. Download below!