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It seems that Moore’s law has been imminently coming to an end for quite a long time. In 1995, the smart money predictions were that once 100nm features were hit (the average was 350nm at the time) it would be game over for Moore. As features continued to shrink, current leaking through transistors in the “off" state was becoming such a stark issue that it could dominate a chip's power consumption.
The problem worried DARPA (the Defense Advanced Research Projects Agency) so much they funded forward-looking research in mid-1995 looking to develop a '25nm Switch'. At the end of the four-year grant term Chenming Hu, a professor of electrical engineering and computer science at the University of California, Berkeley and his team had developed the answer: 3D transistors called FinFETs.
Ironically, it wasn't until 2011 that Intel actually started using the technology on sub-25-nm geometries, as up to that point the existing technology was not ‘broke’ enough for anyone to want to fix it by investing in new technology. Since that time, FinFETs have dominated the microprocessor industry.
The term FinFET comes from the fact that the channel region (the part of the FET the current flows through) is shaped like a vertical fin that protrudes up from the base silicon. The gate then sits over this fin, covering it on three sides to control the flow of current through the channel:
This geometry increases the contact area between the channel and the gate of the transistor by scaling in the vertical direction. That makes for faster switching times and higher current density compared to a flat, planar design.
This is the technology that foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) is betting on for its 3nm process. TSMC has promised a 10% to 15% performance gain (for the same power and transistor count) from this aggressive extreme ultraviolet lithography (EUVL) process over existing N5-based (5nm) products. Users could also see up to 30% power savings (for the same clock speeds), up to a 70% increase in logic density and up to 20% gain in SRAM density.
However, like planar transistors, FinFET transistors eventually reach a point where they cannot scale as process nodes shrink and this is the last die shrink that TSMC has planned for this technology.
In order to scale down further, the relative contact area between the channel and the gate has to increase. This can be done using what's known as a Gate-All-Around (GAA) design. As the name suggests, GAA designs adjust the dimensions of the transistor so that the gate completely surrounds the channel, rather than only on the top and the sides. This means that GAA designs can also stack transistors vertically, rather than just laterally.
Another fabrication titan, Samsung, has already abandoned FinFETs for their 3nm devices. They have gone all-in on a variation of GAAFETs that implements the channel like a horizontal sheet, called a nanosheet. Samsung's trademarked version of this nanosheet tech is called Multi-Bridge Channel FET, or MBCFET.
The beauty of nanosheet technology is the flexibility it affords to vary the “effective width” (or Weff) of the transistor channel. This is the key metric in defining the power and performance characteristics: the wider the channel, the more current you can drive through it for a given voltage, effectively reducing its resistance.
Indeed, Samsung includes four different nanosheet widths in its product design kits (or PDKs - the design rules for the 3nm process), allowing different optimizations within the same chip design: low power designs use narrower nanosheets, while high-performance logic will use wider sheets.
Although still using FinFETs, in a bid to regain a dominant position by 2025, Intel is also developing its own nanosheet technology, trademarked as RibbonFET.
Coupled with the nanosheet architecture in this instance is an ARM developed innovation of back-side power delivery with buried power rails; something Intel is calling 'PowerVia'. All the power delivery interconnections are moved beneath the transistors. This reduces resistance in the power delivery network, which in turn means there's less of a voltage drop from the power source to each of the transistors. It also leaves more space for data-carrying interconnects diminishing the size of logic cells.
The rumour mill is rife with tales of woe (like this from DigiTimes) regarding process yield problems for both TSMC and Samsung. This seems to be backed up by TSMC tinkering with its 3nm processes in a bid for the foundry to find a sweet spot for yield, while Samsung's 4nm Exynos 2200 debut wasn't the expected barnstormer.
Arguably, Samsung has the trickier hurdle to overcome implementing a new transistor architecture but (assuming they can improve yield) this early switch may be a gamble that pays dividends down the road for 2nm, when (for Samsung) it will be an established process.
While the rumours of difficulties may be correct, they should be taken with a pinch of salt. There are always difficulties to iron out when starting a new production process and neither company has publicly admitted any 3nm delays so far. In fact, both claim confidence in their production runs starting in 2H 2022, as predicted. Given the cycle time for a new process is often over 100 days, we will probably see the first product in early 2023.