By Mike Jones
Senior FAE, Micrel Inc.
The roll out of low cost broadband services has led to an ‘IP’ network revolution across factory, office and home. Ethernet has almost exclusively become the physical layer for all networking applications, whether they be industrial control, office routers or consumer equipment such as Home Gateways, VoIP phones or Set-Top-Boxes.
Ethernet has dominated due to the ease-of-use and open standard approach providing true interoperability between equipment in the field. By itself, Ethernet is not strictly a protocol yet it provides the lower ‘hardware’ layers for the higher layer software stacks such as TCP/IP or UDP. So, it would seem the task to network a device should be as simple as ‘bolting on’ an Ethernet transceiver and modifying the software. Indeed, this is basically true, however, the many different interfaces offered by today’s vast number of Processors and FPGAs often adds uncertainty.
So how do I interface my Ethernet PHY (transceiver), multi-port switch or controller to my chosen processor? This depends firstly, if the processor provides an integrated MAC (Media Access Control).
Interfacing to Processors with Integrated MAC
The two basic building blocks in Ethernet are the MAC (controller) and the PHY (transceiver). The MAC-PHY interface comprises of two signal groups; a data bus and a management bus, and is known as the MII (Media Independent Interface). The MII is specified in clause 22 of the IEEE 802.3 standard. This interface is independent of processor and physical media (copper or fibre), providing both simplicity and interoperability.
MII comprises of 4-bit transmit, TXD[3:0], and receive data, RXD[3:0], buses operating from independent 25MHz clocks TXCLK (local clock) and RXCLK (recovered line clock), respectively. Additionally, on the transmit side, TXEN indicates when data is sent by the MAC and TXER indicates if errors have occurred during transmission. Similarly, the receive side uses RXDV to indicate valid data and RXER to signal if physical layer errors are detected. For half duplex operation signal COL indicates a collision during transmission, and CRS signals the presence of data transmission and/or data reception.
When interfacing a multi-port Ethernet switch to a processor using MII then the connectivity is not as obvious due to the MAC-MAC configuration, as shown in the example in Figure 2. The solution is for the Ethernet switch to act like a ‘PHY’, by sourcing both TXCLK and RXCLK. Here the switch is configured to what is known as Reverse or PHY mode.